One of the important issues in modern telecommunication systems is Power Amplifier (PA) linearization. Power amplifiers are inherently nonlinear systems. PA linearization techniques have many problems such as high cost, complexity in design and implementation and bandwidth limitations. Digital predistortion is one the most efficient thecnique for the linearization of RF power amplifiers with memory effect. This thesis presents design and hardware implemntation of a digital predistorter. For this purpose, a memory polynomial structure is used for the predistorter that its coefficients are calculated by using the Recursive Least Squares (RLS) method. In the first step, the performance of the method is evaluated for linearization of a real PA model by using Matlab simulation. In the second step, a floating-point model is developed for the predistorter in the Simulink environment and then the fixed-point model is extracted from it. By simulating the fixed-point model and comparing its results to the floating point model, proper word lengths are obtaind for internal calculations and signals. In the next step, the hardware model of the predistorter is implemented and synthesized by using the System Generator tools. Then, the hardware resources requirements, maximum speed and power consumption of the design for implementation on the FPGA are estimated. The simulation results of the fixed-point predistorter hardware model in the System Generator environment (according to the eligibility criteria such as MER, ACPR and NMSE) show that by choosing the proper wordlength of input/output signals and internal calculations, the performance of the fixed-point digital predistorter is very close to the floating-point model. By analyzing the hardware model of the predistorter for implementation on Virtex-5 FPGA in the System Generator enviroment, the maximum operating frequency of the predistorter with non-modified critical path is 51.85 MHz. By modifying the critical path, the operating frequency of the predistorter increases to 130 MHz. Furthermore, By choosing the appropriate structure for the complex multipliers, the number of hardware resources is reduced. Finally the designed predistorter is implemented on the FPGA and its linearization performance is checked for a real amplifier by using a practical test setup. The implementation results show that the designed predistorter decreases the ACPR value to 5 dB and increses the MER value from 26.1 dB to 33.9 dB. Keywords: Digital Predistorter (DPD), Memory Polynomial (MP), Recursive Least Squares (RLS), Fixed Point Model, Hardware implementation.