Heart diseases are one of the major reasons of death all around the world. One of the most epidemic heart diseases is bradycardia in which patient’s heart pumps abnormally slow. Bradycardia can be healed with an implantable device in human body which is named artificial pacemaker. Due to the importance of health issues, designing an accurate, lightly weighted and low-power pacemaker is still a challenge. The main aim of this project is to study, design and implement the main parts of an artificial pacemaker in VVI mode. Three major parts of an artificial pacemaker including analog, analog-to-digital converter (ADC) and digital parts were implemented. The heart signal was amplified and filtered through a low-noise amplifier, chopper amplifier, low-pass filter and programmable amplifier in the analog part. The analog circuits designed with emphasis on working in sub-threshold region. Output signal of analog part was given to an analog to digital converter which is a SAR ADC with a reasnoble resolution and speed. Various parts of this ADC including binary search algorithm, SAR logic and comparator were implemented in Xilinx ISE software. Output signal of ADC was converted to digital signal for further proccessing. By processing digital signal and detecting heart signal peaks in digital part, the signs of bradycardia can be recognized. One practical peak detection algorithm was chosen and some changes were made on it to enhance capability of the algorithm and decrease the calculations and power consumption. By detection of the slow heart beat, the pacemaker can send out a pulse with a predetermined amplitude and pulse width to the heart, forcing it to pump in a normal manner. Key Words : Bradycardia, Artificial Pacemaker, VVI Mode, Sub-Threshold Region, Chopper Amplifier, Programmable Amplifier, Analog-To-Digital Converter (ADC), Peak Detection Algorithm.
