Supervisor: Dr. Rasoul Dehghani (dehghani@cc.iut.ac.ir) Electrical circuits in biomedical applications contribute to remedy for some diseases such as Epilepsy, Parkinson, and Alzheimer in a faster, easier, and more reliable way. Since these circuits are usually implantable, they must comply with human body features and patient safety rules. Among designing rules for implantable devices, small occupation area and low power consumption are the most significant principles that must be taken into account. The small size of the implanted device causes body tissue damages to be reduced during the implantation, and low power consumption helps eliminate the use of batteries in the circuit. In addition, low power dissipation means lower heat production that is essential for the patients’ health. To reduce power consumption, diverse circuit-designing methods and various signal-processing patterns can be employed. Among these procedures, using Level-Crossing Analog to Digital Converters (LC-ADCs) that sample and quantize the input signal in the amplitude domain (voltage or current) rather than the time domain results in saving power especially in applications, which deal with analog sparse signals such as brain neural signals or signals in the internet of thing. Sparse signals due to having sharp changes in the time domain include extremely high-frequency components. Therefore, using conventional Analog to Digital Converters (ADCs), which use time-domain sampling methods, is not a good choice. This idea can be simply proved by considering the Nyquist sampling rate and the need for using a sampling frequency of at least twice the input signal frequency to reconstruct the original analog signal. In fact, existence of high-frequency components in the analog environment forces the circuit designer to use a high sampling frequency that leads to considerable increase of the power consumption. In LC-ADC architecture, by sampling in amplitude domain, a new sample is generated when the input signal crosses a predetermined threshold level. Thus, in these ADCs, using Nyquist sampling rate is not mandatory, which lessens the circuit power consumption. In this thesis, a high-bandwidth low-power clockless LC-ADC is presented in which the offset-sensitive power-hungry voltage comparators are replaced by just one current comparator. The designed circuit does not need any fixed-frequency clock pulse that reduces both circuit complexity and electromagnetic interferences. In the proposed circuit, a novel up/down counter is designed consisted of both synchronous and asynchronous counters. Owing to having low capacitive loading, the designed counter can be easily driven without any power-consuming buffer. Moreover, the proposed LC-ADC contains a Digital to Analog Converter (DAC), which provides a recursive feedback network. The DAC includes both binary and unit-element architectures without using any passive component. Furthermore, the designed LC-ADC is able to provide various resolutions for different input bandwidths that makes it an appropriate candidate for a wide range of applications. Simulated in a CMOS standard process, the circuit only consumes 580 nW from a 0.5V power supply for converting a 10 kHz analog input signal to digital quantities with the Effective Number of Bit (ENoB) of 10.5 bits. Keywords: Adaptive-Sampling, Sparse-Signal Processing, ADC, Current-Mode Processing, Low-Power Counter