The popularity of information and communication technology increases the demand for more powerful processing and communication systems. Microprocessors, as one of the main parts of information systems, play important role in determining the performance of these systems. As a result, improving the performance and functionality of the processors will have a great effect on the performance of information processing systems. In this thesis, several basic changes to the structure of a general purpose superscalar microprocessor are investigated in order to improve its performance and computational power. The most important changes are: improving the system behavior by employing the reconfigurability and working in single, dual, thriple and quadruple threaded modes based on the number of tasks needed to be executed by the system, change in the management strategy of branch instructions using instruction fetch from both directions of execution, improving the number of executable instructions, removing upper levels of caches and reducing the performance gap between the memory and processor. In this thesis, all of the design and implementation steps and the way of applying the above changes in the processor structure are investigated. In order to quantify the efficiency of the above changes, performance of the proposed processor in performing a set of benchmarks is compared to the performance of some selected processors that represent different families of general purpose processors. Based on the performance results of executing benchmark set, performance of the proposed processor in executing integer benchmarks is better than the selected processors in almost all cases due to the removal of prediction in management of branch instructions and thus reducing of their performance overhead, increasing the number of executable instructions and the ability to extract more parallelism in instruction level and also decreasing the performance gap between processor and main memory. As a result of loop based nature of floating point applications and more locality in their data accesses, the impact of applying the above changes is decreased. The more advanced structure of floating point functional units in selected processors results in their relative superiority to the proposed processor in performing floating point benchmarks. Performance of the proposed processor in performing floating point benchmarks can be improved using newer and more powerfull functional units. Finally, the proposed processor shows acceptable performance in performing benchmark applications and this highlights the impact of applied changes in its structure. Key words: Microprocessor, Superscalar Processors, Reconfigurability, Multi-Thread Processing, Cache Memory.