With recent developments in semiconductor industry, it is now possible to put various components of a system with hundreds of processors, on a single chip. Network on Chip (NoC) has been recently presented as a promising solution to complex on-chip communication problems. NoCs are composed by a set of routers interconnected by communication channels. In direct NoC topologies, each router connects to a module and both are placed inside a limited region of an integrated circuit called tile. Performance, scalability, modularity and communication parallelism make NoCs a promising communication resource for future SoCs. Latency of systems on chip greatly depends on the communication infrastructure. Therefore, using low latency communication structures is inevitable.The general trend of on chip network design includes generation of characteristic graph application, selecting the appropriate processing cores, mapping the tasks of applications to the selected processing cores, mapping processing cores on network on chip tiles, task scheduling, and selection of routing algorithm. Topology and mapping algorithm are two important factors that have great impacts on system’s latency. In this thesis, a new topology with the aim of latency optimization is proposed. This topology is a combination of NoC and bus which can use benefits of both of these architectures. Based on some general considerations, different preliminary topologies were suggested, among them one topology selected as the best topology. In the proposed approach, buses involve in global communications in addition to local communications. A new routing algorithm is proposed that combines XY routing algorithm with the deployment of bus for global communications. A new method for application mapping is proposed for the new hybrid architecture. In this method, cores with heavy affinity are placed in same bus.According to the topology and with the aim of latency reduction, cores are mapped to network on chip topology. The proposed algorithm has two steps. In the first step, partition graph is created and mapped to buses. Partition graph presents the partitions and relations between them. In the second step, cores are mapped to tiles. We use TGFF tool to create task graph. TGFF is one of the most popular tools that is employed for task graph generation and also used in NoC researches. For multiple use-case applications with multiple task graphs, we use average graph, which is created from multiple task graphs. Proposed topology and mapping algorithm was investigated in various task graph sizes. For each test scenario, ten task graphs were generated and the averages results for these graphs are presented. Comparison between the total communications of preliminary topologies shows that our selected topology is the best one. We also investigate our topology Keywords: Network on Chip, Topology, mapping, keyword, System on Chip