With scaling of chip manufacturing technology, process variation- divergence of process parameters from their nominal values - gets worse; on one hand, process variation results in differences in delay and power consumption of the die’s transistors. On the other hand, with advances in technology, designers can put more processor cores on a die, and we could have Chip-MultiProcessors (CMPs). In a CMP, a consequence of within-die process variation is that the individual cores consume different power and offer different maximum frequencies. Therefore, considering a variation affected CMP as a homogeneous one is a wrong assumption. In such a system, if variation not considered in task allocation, the scheduling would be suboptimal. In contrast, if variations observed as an effective parameter in task allocation algorithms, a significant improvement in throughput and power consumption is available. Similarly, ignoring variations in CMP power management, even global-DVFS-based power management techniques, is not best. Instead, DVFS can be performed in per-core manner or in the dynamic voltage/frequency islands. It is significant that such scheduling and power management algorithms can be easily carried out in today’s commercial processors. For example, Intel's Foxton technology for the monitoring and control power of cores is used in their processors. Furthermore, the AMD quad-core Barcelona processor provides per-core frequency assignment. Many techniques are offered to improve the performance of heterogeneous CMPs by optimization of application scheduling algorithms (However, CMP can be designed heterogeneous from the first). These algorithms try to allocate each application to the best-suited core, which run the application in less time and with minimal power consumption. As far as we know, in none of them disrupt the balance of this system is not considered. Indeed, in such methods, some parts of the chip have a great load while other parts are mostly idle. As a result distribution of temperature will be asymmetric at the chip wide, and therefore, we will have hotspots. In addition, leakage power relies on the temperature exponentially and will increase largely. Moreover, passing threshold temperature will activate dynamic thermal management (DTM) techniques, which influence performance dramatically; both cases have been described in. Another issue is that assigning cores for applications due to increasing performance may be opposed with fairness. Due to uniformity of core's capabilities in a heterogeneous CMP, applications execute on cores with different performance. Therefore, scheduling strategy should allow all the applications to use high-performance cores equally as much as possible. In this thesis, we propose a scheduling method for CMPs that in addition to process variation, considers balancing of the CMP in task allocation. Hence, processor resources used fairly, and temperature distributed chip wide. Moreover, to optimize power consumption, per-core DVFS is used. To increase the speed of optimization algorithm, uses of DVFS with very low resolution have suggested which makes the search space small and overheads of finding the voltage/frequency optimal values reduce. Keywords: Application Scheduling; DVFS; Chip MultiProcessors; Process Variation; Power Management; Balancing
