In this research, the architecture of a scalable switch has been proposed. The structure of the design depends on the technology that is being used to implement the switch. In fact, due to the advantages of FPGA (Field Programmable Gate Array) technology, such as availability, low cost and short implementation time with respect to the ASIC (Application Specific Integrated Circuit) design which has limitations such as complex design process and high cost, The FPGA technology has been selected to implement the scalable architecture as a convenient way. Although the FPGA technology has some limitations such as limited number of pins and resources (memory, CPU and etc.) during the design process. Therefore, due to this technology and existing limitations, the architecture of a scalable switch will be proposed and to test the proposed structure (architecture), a switch on a Spartan6 family FPGA platform has been implemented. In this research required resources and design constraints for the implementation of large scale switches on the FPGA platform has been studied. So, we are going to be able to estimate and identify the required resources and their limitations and to choose the right FPGA platform to design and implement large scale switches. The main purpose of the proposed structure in this research is that each of the design blocks, can be implemented on a separate FPGA chip, and then each of these chips based on a proposed design scheme can be hierarchically integrated on a board to make the large scale switch. But, since there is no such a board with such properties, in the first stage of the test process, the whole design theme has been downscaled in which the switching blocks are 5x5 and in two layers makes our switch. In the main structure, the size of blocks will be assigned with respect to the available resources on the FPGA chip. In the following thesis, first it has been tried to study the available solutions to design a switch. Then to reach the goals on designing a scalable switch and to consider the challenges in the design process, a sample hierarchical switch on a FPGA platform has been implemented. The mentioned switch has been implemented on Spartan6 FPGA family boards. Keywords: Switch Architecture, Scalability, Hierarchical, FPGA
