Network-on-Chip (NoC) is an efficient and scalable communication mechanism for integrated circuit chips containing a large number of processing cores. With increasing the number of cores in a chip, the number of NOC routers needs to be increased as well. Since these routers are typically complex and energy hungry, the chip’s power consumption dramatically increases by increasing the number of core (thus the number of routers). On the other hand, the static power consumption of the NOCs is increasing day by day due to the technology advancements in reducing transistors’ dimensions and lowering the operating voltage of the transistors. Nowadays, around half of the NOC power consumption is due to the static power. Moreover, increase in static power consumption makes the chip warmer, leading to even higher power consumption. Therefore, a static power consumption reduction technique is of paramount importance for NOCs. One of the most effective techniques for reducing the static power consumption on a chip is power gating. By turning off the idle network routers in a NOC, a major part of leakage current in routers is avoided. However, applying the power gating technique to the routers of a NOC strongly increases the latency of the packets since they need the routers in the path to turn on. This operation results in a sharp drop in the performance of the chip. Since the performance of the NOC has a huge impact on the overall performance of the chip, an appropriate balance between the power consumption of the chip and its performance is needed. In this research, we propose a technique called ChangeSUB which is an extension to multi-NOCs (catnap). In this method, the control packets are able to change a non-zero subnet to a zero-subnet in a multi-NOC, if there is a virtual channel available in the router of the zero-subnet. Because all the zero-zubnets are always on, the packets can get forwarded through the zero-subnet routers without waiting for them to turn on. It effectively reduces the average latency of packet delivery in the NOC. Based on the results of the PARSEC benchmark, the average latency of packets decreased by 3.03% compared to the base multi-NOC technique. Along with this improvement, 2.1% of the area overhead is imposed. Keywords: Network on Chip, Power Gating, Static Power, High Performance Computing
