In this thesis, histogram based test method is employed to calibrate analog to digital converters (ADCs). A test signal with a known probability density function (PDF) is applied as a calibration signal into the ADC and at the output it is reconstructed. The difference between the known and the extracted output PDFs is a criterion to extract the error parameters of the ADC. After estimation of error parameters, a proper error trimming is performed to compensate for the nonidealities and improve the linearity of the ADC. The proposed calibration method is employed in different ADC topologies including pipeline, parallel pipeline, flash and also a first order Delta-Sigma Modulator ADC. Though, the main focus in the present work is on the flash ADC. Implementation results of an example 4-bit flash ADC show imporovement in the performance of the converter relying on the proposed calibration technique. In this case, the design of the analog parts of the converter is more relaxed and in some sub-blocks of the system such as comparator the maximum possible speed is achieved. Moreover, the analog complexity either is shifted to the digital part of the system in terms of calibration technique or it is exchanged with some simple passive analog elements such as analog switches in the structure. In this case, the implementation of the converter shows more compatibitliy in newer CMOS technologies. Key Words Analog to digital converters, calibration, delta-sigma modulator, flash ADC, histogram, PDF generator.
