In the last few decades, high-level synthesis has stabilized its position in the design automation hierarchy, and due to its capability of accelerating the production of VLSI designs, has found special place in the integrated circuits industry. The high-level synthesis process contains two main phases: scheduling and resource allocation. Resource allocation is further devided into three tasks, which are: register allocation, functional unit allocation and interconnect allocation. In resource allocation phase , and in the process of register allocation, an appropriate storage element is allocated to each variable or signal that exist in the data-flow graph of the circuit. Available options for the storage element are latch and flip-flop. Latches have been used extensively in high performance custom designs, while in ASICs, mostly flip-flops have been used. It’s important to extract higher performance in ASIC designs by employing methodologies used in the custom counterpart. In addition to speeding up the execution of the circuit, latch consumes less power and occupies less area compared to flip-flop. Latch also is capable of tolerating variations in the delay of units caused by process variations. Each of these advantages is a strong motivation to replace flip-flops with latches to upgrade the performance of the circuits. In the filp-flop based designs, each combinational block between flip-flops can be isolated in view of timing, making timing analysis and optimization very convenient for synthesis-based ASICs. This is not the case in the latch-based design, because some combinational blocks may use more than the clock period to compute, which has to be compensated for by some other blocks that use less than the clock period. Due to the complicated timing behavior of latches, their use makes the desig process of the circuits more complicated. This is the case in all levels of synthesis including high-level synthesis. This complicated timing behavior of latches can be made manageable through the operation scheduling, register allocation, and control synthesis; the key idea commonly carried in these HLS steps is to prevent latches from being read and written at the same time while latches are traarent. In this thesis, by using the concept of phase-step, high-level synthesis of latch-based architectures have been presented in the form of VHDL codes. Using this kind of synthesis makes it possible to decrease the delay of the circuit by optimizing the duty cycle of the clock, because the duty cycle, the proportion of the clock being high, affects the phase-step based scheduling, and thus it affects the latency. The method to determine the duty cycle that leads to a schedule of the minimum latency and its code are also presented. The high level synthesis of a latch-based fifth-order EWF filter is presented. The results show compared with its flip-flop –based counterpart structure the execution delay and area of the filter are decreased. Keywords: High-level synthesis, phase-step, latch, VHDL