In this thesis, hardware architectures of point multiplication based on Montgomery ladder algorithm for binary Weierstrass curves(BWCs), binary Edwards curves(BECs) and generalized binary Hessian curves(GBHCs) are presented. The BWCs is implemented in polynomial basis and Edwards and generalized Hessian curves are implemented in Gaussian normal basis(GNB). In the proposed architectures, point addition and point doubling areerformed iarallel by using pipelined digit-serial field multipliers. To maximize the performance of point multiplication for BWCs, a clock switch block is used to manage the clock signal so that the circuit operates at its maximum frequency at different steps of point multiplication algorithm. Also, in this work, an efficient VLSI implementation of point multiplication on BECs by using one multiplier, in 0.18?m CMOS technology is presented. To reduce the area of the circuit, the block of AND gates in the GNB multiplier are implemented by using NAND gates and based on the property of the XOR gates in the XOR tree. Also in the multiplier structure, to optimally decrease the delay, the logical effort method is employed as an ef?cient method for sizing the transistors. The results show that the proposed structures have better execution time and performance compared to previous designs. Key Words Elliptic curve cryptosystems, Point multiplication, Finite fields, Hardware implementation.
