roadband networks satisfy the need to carry integrated traffic involving different types of information such as voice, video and data. Furthermore different services with multiple requirements need specific capabilities to be provided and guaranteed by broadband networks. The architecture of next generation networks has an important effect on making changes in broadband networks and provides these capabilities. On the other hand, the architecture of broad band networks is highly affected by high speed switches. In fact, high speed switches are the target technology to achieve the required capabilities. The performance demands and changes in IC and VLSI technology have led to emergence of different types of switch architectures. The function of switches is to make routing decisions and forward the packets from input to the appropriate output. It is possible that multiple arriving packets from different input ports have to be routed to the same output port because the incoming traffic is not scheduled to have regular behavior. To deal with the output contention, switch system uses different types of architectures. In first generation switches, input ports and output ports were connected using a simple shared bus. Therefore, accessing the shared bus became the main bottleneck in switching systems. Croar switches have overcome this problem using N pair inputs and outputs in parallel. However, implementing croar switches is very expensive. As a result, different types of multistage switch architectures are proposed to reduce the cost of switch design. Switching systems in multi-plane and multistage architectures is based on making different stages which are connected through lots of wires. Not only these wire connection leads to a delay in the entire communication system but also they are more expensive than implementing memories as buffers, from hardware implementation point of view. Shared memory architecture has also its difficulties. A shared memory switch has to operate faster than input data rate because input ports are time multiplexed to shared buffer. However, reducing access time to the shared memory is physically restricted. In addition, the main area of the chip is occupied with shared memory and its related circuits. So, shared memory switch architecture would be expensive, from hardware implementation point of view. In this thesis, we develop a novel architecture by merging the remarkable properties of multi port memories as well as interleaved memories to achieve the advantages of both architectures. To overcome the cost of multi-port memories, we use available low price FPGAs and their internal block RAMs as the main component for constructing dual port memories Considering various switch design alternatives, studying and analyzing of multiple options and exploring advantages and drawbacks of each solution to design a high switch fabric is very important. Each solution has its own advantages and drawbacks, in terms of performance, latency and scalability. On the other hand, shared buffer architecture has high buffer utilization because of sharing a large memory between all input ports. However most packet buffer designers prefer input buffering due to its ease of implementation, shared memory architecture makes possible high switch throughput and it also presents low cell loss probabilities. At first, a survey on designing high speed switch alternatives and their available solutions are done in this thesis. Also, this thesis proposes the architectural details of an scalable, high speed shared memory switch fabric which is operating at 20 G. The presented architecture is implemented using FPGA technology based on Xilinx's Virtex 4 family. The rate of the proposed switch is 173/575 MHz. Keywords: witch Architecture, Shared Memory, Memory Banks, Linked List, FPGA