In the process of design and fabrication of integrated circuits it is very important that the circuits be testable and tested at different stages of IC production, to make sure that they work properly. With ongoing growing of integrated circuit sizes, the design and fabrication of VLSI circuits is becoming more complicated, as well as, the test vector generation and testing of the circuits which are very time consuming and costly, and in some case even impractical. So it is very important to find new techniques of test vector generation which are not only precise but also low complex. For higher level descriptions of circuits the test vector generation is simpler. This indicates generating test vectors for RTL description level is easier than that of gate description level. In this work, for test vector generation of logic circuits first an algorithm implemented in VHDL language is presented. The algorithm that can be used for all description levels of the circuits, finds the smallest test vector set of the circuits with high fault coverage. Stuck-at-0 and stuck-at-1 faults are modeled in the algorithm. Then, another algorithm which works based on controllability and observability parameters of the circuit nodes is presented. This algorithm which is more practical and can be used for larger circuits is employed for gate level description of circuits. This algorithm which is also written in VHDL language first calculates the controllability to 0 and to 1 values of the circuit nodes, and then based on that, finds appropriate test vectors for the circuit. Both algorithms are applied on some test circuits and the results are presented. Spectral analysis can be used to simplify test generation. Spectral analysis of a digital signal is to find its properties and sequences. A digital circuit if considered as a black box can be identified via its input and output signals. Accordingly, test vectors generated for register level description faults have properties that can be used to reveal some characteristics of the gate level structure of the circuit. These properties can be extracted through spectral analysis and used in generation of gate level test vectors. By using spectral analysis and Walsh transform a digital signal is decomposed into a set of unique bit streams of orthogonal functions in which magnitude of each coefficient of bit streams shows the amount of correlation exist between the digital signal and the corresponding bit stream. By maintaining the prominent coefficients and changing nonessential coefficients a new set of coefficients are obtained. By applying reverse Walsh transform to this set of coefficients some new test vectors are generated. These vectors are appended to the primary test set. The new test vector set, even though is originated from a RTL level vector set, shows high fault coverage for gate level faults. By using the algorithm presented in this work, for some test circuits different test vectors for different number of faults in RTL level description are generated and based on them and through spectral analysis new test vectors are generated and fault coverage improvement is calculated. The results are presented and the influencing factors on the improvement are discussed. Keywords: Digital signal, test vector, spectral analysis, testability, VHDL