Nowadays, by rapid expansion of CMOS cameras, and increasing tendency towards system on chip (SOC) architectures, design of smart vision chips using CMOS technology has become very attractive. Smart vision chips are employed in many different applications, including in security and surveillance systems, industrial machine vision, robotics, navigation, traffic control systems, smart medical systems, and mobile communication systems. Smart image sensors not only take images but also do some image processing on them. They use analog and digital processors on the image sensor focal plane to perform image processing algorithms. The digital imagers are more attractive compared to their analogue counterparts because of their lower power consumption, lower cost, higher degree of on-chip integration, lower sensitivity against noise, robustness against supply voltage and process parameter variations, wider dynamic range, higher accuracy, and more on-chip functionality. Each pixel of a smart digital imager consists of a photo detector, an analog-to-digital converter (ADC), a storage block, a processor and a control unit. The converter that converts the analog photo-generated current into its equivalent digital value has an essential role in the sensor performance. It determines the performance by defining the dynamic range, imaging speed, and camera resolution. In general, the light converter should be fast with low power consumption, low area, and wide dynamic range to be usable in the new digital image sensors. In this dissertation, first a general survey on the analog and digital smart vision chips is done. Then, an analog smart image sensor based on cellular neural network (CNN) structure is designed. In the sensor, by using analog circuits on the focal plane, a CNN based noise reduction algorithm is implemented. Then, the existing digital pixel sensors and light converters and their weaknesses are studied. Following that, three high performance digital pixel sensors (DPS) by employing new pixel-level converters are proposed. The converters operate at low supply voltage, and offer low power consumption, low area, wide dynamic range, and high sensitivity. The first proposed DPS is designed based on pulse frequency modulation (PFM) scheme using a new light-to-frequency (LFC) converter. The proposed LFC has lower power consumption, wider dynamic range, and lower area compared to those of previous ones. Additionally, its sensitivity against light intensity is higher than previous works. The second DPS works based on pulse width modulation (PWM) technique, and it employs a novel light-to-time converter (LTC). The proposed LTC consumes lower power and lower area compared to the previous ones. Additionally, it converts a wide illumination range with a high speed. The third proposed Digital pixel is designed by using the proposed LTC and using the concept of the thresholding and time-multiplexing algorithms. In the design, the in-pixel multi-bit counter/memory is eliminated and each pixel has just one memory cell. Therefore, the sensor resolution and fill-factor are improved. In the proposed imager, the memory and process units of pixels are transferred to the outside of the sensor array. The structure is suitable for designing high speed and wide dynamic range general-purpose smart vision chips. The proposed image sensors have been designed and fabricated in a standard 180-nm CMOS technology. The results show that the proposed sensors have higher performance compared to previous ones. Keywords: Low-power CMOS image sensor, digital pixel sensor (DPS), pixel-level analog-to-digital converter (ADC), light-to-frequency converter (LFC), light-to-time converter (LTC), high speed imaging, wide dynamic range imager.