In today's advanced fabrication technologies implementation of a complete system with high processing speed and low consumed area, on a single chip is possible. But for implementation of some operations like multiplication due to the number of needed transistors, and also the overall circuit power dissipation, the challenge still exists and the design of such circuits is critical. In dynamic circuits, the excessive loading of clock signal that connected to the flip flops and dynamic gates, leads to high power consumption especially in high frequency circuits. In Data Driven Dynamic Logic structures (D³L family), compared to other dynamic logic families the clock distribution network is reduced, and instead of clock signal the input signals are used to control the precharge and Evaluation phases. This, not only reduces the problems caused by the clock signal buffering and clock routing, but also reduces the power losses in the circuit. However, along with less power consumption compared to other dynamic structures, the precharge and also often the evaluation phases are slower in D³L structure. Therefore the structure needs some modification to reduce the problem of low speed. Today, in every general purpose microprocessor structure, a part of the hardware is allocated to the divider section. Also in the processing of digital signals in the three dimensional graphic applications, high speed units that perform division operation are necessary and the demand for them is increasing. In general, the sequential format of the division operation leads to high latencies in the circuits. Using high radix numbers, especially in the SRT dividers which are considered among the fastest division algorithms in VLSI circuits, reduces the number of steps efficiently, that consequently reduces the latency and subsequent power consumption. Using look-up table to select the quotient, which is performed in most algorithms, has lead to the complexity of the SRT dividers implementation, causing that a considerable part of the consumed power be related to the tables. Employing some methods to reduce the size of the tables, or even remove them, can considerably increase the speed of the divider and also reduce the power consumption. In this thesis besides reviewing the division algorithms and the logic families' structures, the implementation of a 16bit radix-4 SRT divider based on a modified D³L family structure is presented. The aim of the work is reduction of, the required steps to perform the algorithm, latency, delay, and power consumption. For implementation the TSMC_180 nm technology is used. The divider has pipelined structure and its latency is equal to 10 half cycles. Key Words: SRT dividers, Latency, Data Driven Dynamic Logic Structures, Reduction of energy consumption, Speed.