: Pipelined Analog to Digital Converters (ADCs) are used extensively in high-speed and high-resolution applications such as wireless communications, video and graphics and image recognition. In this architecture like most of analog systems, there is a strong trade-off between speed and resolution, so finding the ways to moderate this trade-off is one of the main challeneges in the literature. Time interleaving structures have the advantage of increasing the throughput rate of PADCs, however they suffer from many problems due to the time multiplexing and mismatching of the channels that significantly limit the effective bandwidth of the input signal. Recently digital calibration methods have been proposed to moderate the above mentioned speed-accuracy trade-off by shifting the analog complexity into a digital section. It allows imperfect design to have a high speed structure, and post processing to increase the resolution. Obviously, sacrificing the other two main ADC factors (power and area) may happen which is tolerable in many applications. This thesis presents a background calibration technique in which linear and offset errors are digitally measured and eliminated. The proposed structure keeps the nonlinear errors in low values; moreover the algorithm is easily extendable to cover this source of error. The proposed technique utilizes a single algorithm and works in real-time without tampering with analog signal paths which is inevitable in many conventional approaches. Consequently the proposed .
