This thesis will present a novel solution for efficient hardware implementation of point multiplication in elliptic curve digital signature. In all three phases of signature including key pair generation, running signature and its verification, point multiplication on elliptic curve is the most time-consuming operation. So we will provide some solutions to optimize point multiplication which compose of two sub-operations, point addition and point doubling. Regarding fast implementation, we selected binary finite fields in comparison with prime fields. In these fields there is need to implement add, square, reduction, multiplication and inversion. Since inversion consumes much more time than the other operations, it is usual its alternation with other operations via converting coordinates from affine to projective one. Due to imposing fewer operations to the scheme, we use Lopez-Dahab projective coordinate. Thus scheme's bottleneck will simply be polynomial multiplication. We provide some solutions to accelerate the scheme without any needs to much more space. Used platform to implement the scheme is FPGA, Virtex2 XC2V2000 with a binary finite field of degree 163 proposed by NIST. Based on this selection, we have presented an efficient reduction of O(1). Proposed architecture for squaring has O(1) without any need to reduction after obtaining result. Add is another high consumption operation that is implemented of O(1). Finally regarding to space limitation, polynomial multiplication, as a main operation, is proposed of O(n) without any need to consequent reduction like squaring. Using these architectures, Lopez-Dahab projective coordinate and a NAF solution to reduce the number of bit 1 in polynomial strings, our proposed scheme can fulfill point multiplication in 65 micro seconds with a 195 MHz clock pulse. Keywords: Digital signature, hardware implementation, algorithm optimization, point multiplication, finite fields
