Today, the incredible growth in the use of electronic devices that require DC power supplies leads to employing more and more rectifiers. Since diode rectifiers include diodes and capacitor, DC power supplies draw nonsinusoidal current from power line and pollute line current by harmonic components. Therefore, power factor (PF) decreases and total harmonic distortion (THD) increases. Also, Harmonics in power systems cause overheating in transformers and induction motors and electromagnetic interference. In order to minimize the power grid damages resulted by injected harmonics and achieve high power factor in electrical equipment, standards such as IEC61000-3-2 should be met. Thus, researchers have focused on improving power factor correction (PFC) topologies. The boost converter is widely used as a PFC converter due to its high PF and simplicity. However, boost converter cannot provide low output voltage. Thus, due to inrush current problem and the required low output voltage in some applications such as server, telecommunication, storage systems and networking, the researchers have introduced buck type PFC converter. In bridgeless technique, input bridge diode and PFC stages are merged together to reduce the number of simultaneously conducting semiconductor devices. In this thesis two bridgeless buck PFCs are introduced. The main drawback in the buck type PFCs is existence of dead angle when the output voltage is higher than input voltage, which leads to high current distortion and low PF. Therefore, in the first proposed PFC an auxiliary switch and in the second proposed PFC a Flyback converter are employed to omit dead angle from input current and improve PF. All of two proposed PFCs operate under DCM condition and shape input current inherently. Due to elimination diode bridge, the minimum number of semiconductor devises is applied in the power flow path that decreases conduction losses. Furthermore, all semiconductors turn on and off under soft switching condition. Laboratory prototypes of the proposed bridgeless PFCs are designed and implemented to verify validity of theoretical analysis. It is concluded that proposed bridgeless PFCs omit dead angle of input current and reduce THD. Also, due to reduction of the number of semiconductors in the power flow path and providing soft switching condition for semiconductors, efficiency of proposed bridgeless PFCs are high and equal to %92. Key words: Bridgeless Buck PFC, Dead Angle, Soft Switching
