With the advancement of technology in recent decades and increase of integrated circuits density, the importance of the power consumption parameter in design of electronic circuits is steadily increasing. GDI is one of the logic structures introduced to design low-power logic gates. In this structure, the design of complex circuits can be done with less number of transistors and with less power consumption. The structure reduces leakage losses due to its special topology. As the threshold voltage decreases in new technologies, leakage losses increase exponentially and account for major part of total losses, so reducing these losses will have a significant effect on the overall power consumption of the circuits. In some applications in signal and image processing, like machine vision and machine learning, if there are some inaccuracies in calculations, the system still has capability of producing output in an acceptable accuracy range. In these applications, design and use of unnecessarily accurate computational units leads to high complexity of circuits and increase of power consumption. Among the four basic and widely used computational units, division unit has most complexity. Design improvement of this unit has a significant impact on the overall power consumption, latency and area of the systems. In this thesis with the aim of reduction of the complexity of this unit, by using the GDI structure several approximate dividers with different accuracy levels have been investigated, designed, and implemented in 45 nm technology. Simulation results show that the dividers in GDI structure compared to their CMOS counterparts have 69% lower power consumption, 33% lower delay and 63% lower area. Simulations results show that the GDI structure is less sensitive to temperature variations, but is more sensitive to the process corners, compared with CMOS structure. Some typical methods, like logical effort, used to optimize the sizes of transistors in CMOS structures to reduce the delay, cannot be used in GDI structure. In this structure, successive stages are not isolated in terms of current, creating a Capacitive-Resistant Chain. Extending this chain and also connecting a large output load to it will increase the delay of the circuit. By using a derived delay equation, the sizes of GDI cells are optimized for minimum delay. To evaluate the efficiency of the proposed approximate dividers in image processing applications, they were used in implementation of JPEG algorithm. Results show that in most cases, the error resulting from the approximate dividers is small. Reduction of hardware complexity and power consumption of approximate dividers in these applications will reduce the total delay and power consumption of the system. Keywords: Digital System, Low Power, Gate Diffusion Input (GDI), Approximate Divider