Nowadays image processing has attracted much attention, especially in design of real-time image processing systems because of the need for high speed, along with low area and low power consumption features. Vision chips are developed to achieve these requirements where the main idea is mostly to integrate the image sensor section and the processing circuit on a single chip, mostly in a CMOS technology. In terms of implementation, vision chips are divided into three categories of digital, analogue and mixed mode. In terms of application, they can be divided into general and specific purpose chips. The digital vision chips have normally the benefits of higher speed, precision, stability and noise immunity, but their analogue counterparts have lower power consumption and occupy smaller area. Since multitask vision chips have the capability of programmability, and are able to accomplish various signal processing tasks, these chips have higher power consumption. They also occupy more area and offer lower speed and lower fill factor comparing to the specific purpose chips. The aim of present work is to design a multitask digital processing circuit, wich performs in-pixel processing in high speed, and with low power consumption, and it has a relatively high fill factor. For the processings which can be performed in a parallel an SIMD architecture is used. The processings such as erosion, dilation, edge detection and combination of them are performed synchronously in each pixel and in parallel, so the processing time is independent of the image size. Another processing that the proposed circuit performs is asynchronous propagation among the pixels that is used for the hole filling and image reconstruction. The speed of this processing is dependent on the image size and the state of the propagation. In the proposed circuit each main synchronous processing is performed in one clock cycle that causes a relatively high increase in the processing speed. This means that the frame rate is equal to the working frequency. In the proposed circuit a dynamic comparator is used in each pixel. The designed layout for one pixel shows the fill factor i about 27.5 %. The simulation and experimental results of an array of 32 64 of the proposed pixel verify the performance of the circuit. Keywords: 1- Vision chip 2- CMOS smart image sensor 3- In-pixel processing 4- Multitask processing 4- Fill factor