In the process of electronic circuits design it is necessary to estimate various parameters, so that based on them an appropriate circuit can be selected. The most important parameters are speed, power consumption and area. The speed parameter can be estimated by using some models for transistors and gates. These models, besides simplicity, need to be enough accurate in order to give an accurate estimation of circuit behavior. Using a simple and appropriate model is important because it can help to estimate the delay before the simulation step and before accurately designing the circuit, and also can help to find appropriate topologies to decrease the delay. Logical Effort is a simple model that can rapidly estimate the delay of the circuit with enough accuracy. By using this model the minimum delay can be estimated only by knowing the number of the stages, the path effort parameter, and the parasitic delay of the logic gates. Therefore, it can be done before determining the sizes of the circuit gates. The sizes can be determined later based on the estimated delay. Another advantage of the model is that the delay calculation is independent of technology and manufacturing process. With recent rapid advances in multimedia and communication systems, real-time signal processing has found high importance in many applications. Adders are used as fundamental building blocks in many digital processors. So, their speed has important role in the processors speed. A typical structure of an adder is the Ripple Carry Adder. The delay of this adder is mainly due to the generation and propagation of the carry signal from the lower bit to the higher bits. Many techniques have been proposed to decrease this delay. Multiplier units are also widely used in many digital processing systems. Improving the speed and performance of this unit effectively increases the speed of the system. In fact, the highest operation time, within the basic digital operation units, usually determines by the multiplier units. Therefore, designing a fast multiplier to achieve high speed processing units for today’s applications will be important. Column compression multipliers such as Dadda and Wallace structures are among the fastest multipliers. In these two structures the delay is proportional to the logarithm of the operand word length. In the array multipliers this dependency is linear and as a result the delay is much higher. The two structures also have lower hardware and area. In this thesis first a 64-bit Carry Look-ahead Adder is designed and then its Keywords: 1- delay models 2- critical path 3- logical effort 4- ripple carry adder 5-carry look-ahead adder 6- column compression multipliers