Today, vision chips have many applications in real time image processing. By integrating the image sensor and processor(s) o one substrate, the data transfer bottleneck between these two parts has been removed, and as a result the chips are capable of performing image processing algorithm at very high frame rates (in order of thousands frames per second). Different types of vision chips each with its own pros and cons have been proposed and fabricated, and are categorized based on different parameters. For instance, they can be categorized based on their circuit structures, as analog or digital vision chips. Digital vision chips are faster, more robust and more tolerant to the noise. On the other hand analog ones consume less power and are more compact. Processors arrangement is another parameter used to group these chips. Processors can be located next to each pixel, or next to each column(row) of pixels, or next to entire pixels array. Pixel-level processors are the fastest but they are extremely large and reaching to high-resolution images are impossible with them. In contrast, chip-level processors are a good choice for high resolution images, but they are relatively slow. Column-level processors are located between these two limits. In this work a general-purpose vision chip based on column processor is proposed. The vision chip uses SIMD structure for its image parallel processing. By using digital processors, the chip can process black and white (binary) and gray (8 bit) images. Image algorithms implemented in this chip are low-level, and include: spatial filter with a 5×5 kernel and with arbitrary coefficients, like edge detection and averaging; ranking or statistical filter, like median, maximum and minimum filters; and morphological filter including erosion and dilation. By exploiting a global memory, the chip area is reduced, and also performing high frame rate image processing tasks is possible . The processing is done in a bit-serial manner due to the large size of the kernels. The proposed structure can be easily developed for doing other tasks. There is a processing element(PE) and it’s corresponding circuit for each 5 column of the pixels array. Therefore the size of the chip is proportional to the number of image columns, while the processing speed is proportional to the number of images rows. For example it takes 40µs and 4.8µs to process an image with 64 rows in gray and binary mode respectively. The proposed circuit is implemented using both full-costum design and digital design flow manner. The SDF files are used for time verification of the circuits. The results related to design, implementation and simulation of a 64×64 array verifiy the functionality of the circuit. Keywords: 1-vision chip 2- CMOS image computing sensor 3-VLSI 4-row/column processor 5-image processing 6-SDF Files